// Copyright (C) 1953-2021 NUDT
// Verilog module name - share_buffer_input.v  
// Version: V4.0.20220526
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         port receive process
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module share_buffer_input #(parameter inport = 6'b000000)
    (
        i_clk,
        i_rst_n,
        
        i_data_wr,
        iv_data ,
        
        iv_addr             ,      
        iv_wdata            ,
        i_wr_psc            ,
        i_rd_psc            ,
        i_wr_pdg            ,
        i_rd_pdg            ,
                                     
        o_wr_psc            ,
        ov_addr_psc         ,
        ov_rdata_psc        ,                                       
        o_wr_pdg            ,
        ov_addr_pdg         ,
        ov_rdata_pdg        ,
                          
        i_rc_rxenable       ,
        i_st_rxenable       ,

        i_hardware_initial_finish,

        i_pkt_bufid_wr      ,
        iv_pkt_bufid        ,
        o_pkt_bufid_ack     ,

        o_md_wr  ,
        ov_md    ,
        i_md_ack ,

        ov_pkt,
        o_pkt_wr,
        ov_pkt_bufadd,
        i_pkt_ack,
        o_pkt_rx_finish,
        iv_free_bufid_fifo_rdusedw,
        iv_hpriority_be_police_threshold,
        iv_rc_police_threshold,
        iv_lpriority_be_police_threshold
    );

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n;
//GMII RX input
input                   i_data_wr;
input       [8:0]       iv_data ;

input       [18:0]      iv_addr;                         
input       [31:0]      iv_wdata;                        
input                   i_wr_psc;         
input                   i_rd_psc;         
input                   i_wr_pdg;                        
input                   i_rd_pdg; 

output                  o_wr_psc;          
output     [18:0]       ov_addr_psc;       
output     [31:0]       ov_rdata_psc; 

output                  o_wr_pdg;                     
output     [18:0]       ov_addr_pdg;                  
output     [31:0]       ov_rdata_pdg; 
//configuration
input                   i_hardware_initial_finish;
input                   i_rc_rxenable                   ;
input                   i_st_rxenable                   ;
//pkt bufid input
input                   i_pkt_bufid_wr;
input       [8:0]       iv_pkt_bufid;
output                  o_pkt_bufid_ack;
//descriptor output
output                  o_md_wr ;
output      [299:0]     ov_md   ;
input                   i_md_ack;
//user data output
output      [133:0]     ov_pkt;
output                  o_pkt_wr;
output      [15:0]      ov_pkt_bufadd;
input                   i_pkt_ack;  

input       [8:0]       iv_free_bufid_fifo_rdusedw;
input       [8:0]       iv_hpriority_be_police_threshold;
input       [8:0]       iv_rc_police_threshold;
input       [8:0]       iv_lpriority_be_police_threshold;
output                  o_pkt_rx_finish;
// internal wire
wire        [8:0]       wv_data_psc2pdg     ;
wire                    w_data_wr_psc2pdg   ;
wire        [15:0]      wv_eth_type_psc2pdg ;
wire        [2:0]       wv_pkt_priority;

//wire        [1032:0]     wv_pkt_pdg2ibi;
//wire                    w_pkt_wr_pdg2ibi;
//wire        [8:0]       wv_pkt_bufid_pdg2ibi;
//wire                    w_pkt_bufid_wr_pdg2ibi; 
  
  
port_state_control port_state_control_inst(
.i_clk                            (i_clk                          ),
.i_rst_n                          (i_rst_n                        ),

.i_rc_rxenable                    (i_rc_rxenable                  ),
.i_st_rxenable                    (i_st_rxenable                  ),
.i_hardware_initial_finish        (i_hardware_initial_finish      ),                                                          
.i_data_wr                        (i_data_wr                   ),
.iv_data                          (iv_data                    ),
                                                                
.iv_addr                          (iv_addr                        ),                         
.iv_wdata                         (iv_wdata                       ),                        
.i_wr_psc                         (i_wr_psc                       ),         
.i_rd_psc                         (i_rd_psc                       ),         
                                                                  
.o_wr_psc                         (o_wr_psc                       ),         
.ov_addr_psc                      (ov_addr_psc                    ),      
.ov_rdata_psc                     (ov_rdata_psc                   ), 

.ov_data                          (wv_data_psc2pdg                ),
.o_data_wr                        (w_data_wr_psc2pdg              ),
.ov_eth_type                      (wv_eth_type_psc2pdg            ),
.ov_pkt_priority                  (wv_pkt_priority                )
);    

packet_digest_generate #(.inport(inport)) packet_digest_generate_inst(
.i_clk                            (i_clk),
.i_rst_n                          (i_rst_n),
                                  
.iv_addr                          (iv_addr),                         
.iv_wdata                         (iv_wdata),                            
.i_wr_pdg                         (i_wr_pdg),                        
.i_rd_pdg                         (i_rd_pdg), 
                                  
.o_wr_pdg                         (o_wr_pdg),                     
.ov_addr_pdg                      (ov_addr_pdg),                  
.ov_rdata_pdg                     (ov_rdata_pdg), 
                                  
.iv_data                          (wv_data_psc2pdg),
.i_data_wr                        (w_data_wr_psc2pdg),
.iv_eth_type                      (wv_eth_type_psc2pdg),
.iv_pkt_priority                  (wv_pkt_priority),
                                  
.i_pkt_bufid_wr                   (i_pkt_bufid_wr),
.iv_pkt_bufid                     (iv_pkt_bufid),
.o_pkt_bufid_ack                  (o_pkt_bufid_ack),
                                  
.ov_pkt                           (ov_pkt       ),
.o_pkt_wr                         (o_pkt_wr     ),
.i_pkt_ack                        (i_pkt_ack    ),
.ov_pkt_bufadd                    (ov_pkt_bufadd),

.o_md_wr                          (o_md_wr ),
.ov_md                            (ov_md   ),
.i_md_ack                         (i_md_ack),          
.o_pkt_rx_finish                  (o_pkt_rx_finish     ),                               
.iv_free_bufid_fifo_rdusedw       (iv_free_bufid_fifo_rdusedw      ),
.iv_hpriority_be_police_threshold  (iv_hpriority_be_police_threshold ),
.iv_rc_police_threshold            (iv_rc_police_threshold           ),
.iv_lpriority_be_police_threshold  (iv_lpriority_be_police_threshold )       
);

endmodule